The present invention relates to demodulation circuits, and more particularly to a digital phase-locked loop circuit that generates a local clock signal that is phase-locked to a carrier signal modulated by amplitude shift keying (ASK). Once such a phase-locked clock signal is generated, it can be efficiently used to accurately demodulate the ASK signal.
Modern communication channels utilize a variety of modulation schemes for passing information on a carrier signal from one location to another. One common modulation scheme, for example, is amplitude modulation (AM). An AM signal is one wherein the amplitude of the carrier signal changes as a function of the information to be transferred. Where the information to be transferred is presented in binary form--having one of two possible values--an AM carrier signal thus assumes one of two amplitudes depending upon the particular binary information that is to be transmitted. Hence, where the binary information may be described as being a "1" or a "0", an AM carrier signal modulated with such binary information assumes a first peak amplitude corresponding to the transfer of a "1", and a second peak amplitude corresponding to the transfer of a "0".
One particular form of binary AM modulation involves making one of the two amplitudes of the carrier signal a known value, and making the other of the two amplitudes zero. In such a case, the transfer of a "1", for example, is indicated by the presence of the carrier signal, and the transfer of a "0" is indicated by the absence of the carrier signal. (These roles could, of course, be reversed, with a "1" being indicated by the absence of the carrier signal, and a "0" being indicated by the presence of the carrier signal.) Such a modulation scheme is a simple form of amplitude shift keying (ASK), wherein the amplitude of the carrier signal shifts between one value and zero. That is, the carrier signal is keyed on and off, as the binary information transferred shifts between one value and another.
ASK has long been a preferred type of modulation for many applications because of its simplicity. More recently, in the implanted device telemetry art, the use of duobinary modulation has been proposed in order to allow a high bit rate to be transferred efficiently (at a low signal-to-noise ratio) through the limited bandwidth channel existing between an implantable device and a non-implantable device, such as between an implantable pacemaker and its corresponding external (non-implanted) programmer. See Applicant's copending patent application, Ser. No. 07/391,080, filed 08/08/89, entitled "High Speed Digital Telemetry System Implantable Device." As indicated in that patent application, the reception of a duobinary encoded signal results in an ASK signal that must be demodulated in order to extract the digital data information therefrom. Advantageously, such ASK signals may be asynchronously demodulated using very simple inexpensive passive demodulation circuits, e.g., comprising a diode, a resistor and a capacitor. Unfortunately, while simplicity and low cost are highly desired characteristics for a demodulation circuit used with implantable devices, such asynchronous demodulation is generally not suitable for use in the high bit rate implantable device art because of the low bit error rates that such implantable device art demands. Hence, there is a need in the implantable device art for a simple synchronous demodulation scheme that can easily, accurately, and inexpensively demodulate ASK signals at low bit error rates. (The "bit error rate" is a measure of how many errors occur as digital information is passed from one location to another. A low bit error rate indicates few errors occur, and is preferred for reliable transmission.)
It is well known in the telemetry art that the bit AM error rate can be dramatically improved using a synchronous demodulation scheme. In a synchronous demodulation scheme, a local, noise free, clock signal is generated that is "phase-locked" to the received carrier signal. By "phase-locked" it is meant that the frequency of the local clock signal is the same as, or integrally related to, the frequency of the carrier signal; and that the phase of the clock signal, typically measured at the data transitions, maintains a fixed known relationship relative to the phase of the carrier signal, typically measured at the zero crossings of the carrier signal. With a noise free clock signal phase-locked to the carrier signal, a synchronous demodulator can easily be used, as per known art. Usually, it is a multiplier having the received signal at the analog input and the regenerated clock at its digital input.
A phase-locked clock signal is typically generated using a phase-locked loop (PLL). A PLL generally includes a voltage controlled oscillator (VCO) that generates a local clock signal having a frequency proportional to a control voltage. The phase error between the clock signal and the carrier signal is measured in a phase detector circuit. The resulting phase error signal is then used as the control voltage to change the frequency of the VCO by an amount that minimizes the phase error between the two signals, thereby phase-locking the clock signal to the carrier signal. (Note that an instantaneous change in the frequency of the clock signal changes its phase.)
One of the problems associated with ASK signals, and the main problem that leads to unacceptably high bit error rates, even when synchronous detection is used, is that the ASK signal may include long sequences when no carrier signal is present. That is, if a digital "1" is represented, for example, by the presence of the carrier signal and a digital "0" is represented by the absence of the carrier signal, and if the digital word "0100000" is transferred using ASK modulation, 5/8 of the transferred word is represented by no carrier signal. During this time, a PLL or equivalent circuit is seeking a carrier signal to lock to when in fact no such signal is present. Hence, during such times when the carrier signal is absent, the locally generated clock signal locks on noise, causing the clock signal to jitter and to assume an erroneous phase relationship relative to the bit times of the data, thereby resulting in an incorrect decision as to the value of a given bit.
To overcome the problem created by long sequences of no carrier signal, the prior art teaches using a modulation scheme that avoids such sequences. For example, frequency shift keying (FSK) and/or phase shift keying (PSK) both include a transition in the carrier signal regardless of whether a "1" or a "0" is being represented. Hence, the carrier signal is always present, and the PLL always has a data transition on which a clock signal can be phase locked. Unfortunately, however, for some applications, e.g., the implantable device art, FSK or PSK modulation may not be preferred because, e.g., the available bandwidth of the communications channel does not allow an efficient transfer of data using these types of modulation. For other applications, while FSK or PSK modulation may be preferred for the transmission channel, processing of the received data when encoded using a duobinary encoding scheme nonetheless results in an ASK signal that must still be demodulated, as indicated in applicant's referenced patent application, "High Speed Digital Telemetry System for Implantable Device." Thus, for such applications where ASK signals are used, or otherwise result from the processing of the transferred signal, what is needed is a synchronous demodulation system that is not adversely affected by a long sequence (e.g., several sequential bits) of the absence of the carrier signal.
Another solution to the problem of long sequences of no carrier signal in an ASK signal is to use a bit encoding scheme that does not permit more than one or two bits of the same value to be transmitted sequentially. Such encoding schemes are well documented in the art and are commonly used in more sophisticated communication channels in order to measurably improve the bit error rate. However, such improvement is achieved only at the expense of more complex encoding and decoding systems. For the implantable device art, where simplicity and low cost are major factors influencing the type of circuits that are used, such complex and sophisticated bit encoding schemes are generally not practical. What is needed, therefore, is a simple and reliable synchronous demodulation system that is not dependent upon a particular encoding scheme that limits the number of consecutive 1's or 0's that may occur in the transmitted data.